As is well known, continuous innovation in the manufacturing technology of semiconductor integrated circuits has made it possible to achieve levels of integration which reduce the semiconductor area occupied by each individual circuit to a minimum, thus increasing the number of circuits which can be integrated on a single chip. One of the limiting factors for the application of such reduced levels of integration is that the circuits obtained in this way are only able to operate with low levels of current and voltage. These circuits cannot therefore be directly interfaced with power systems or load devices operating with high levels of voltage or current.
In the last few years a technology similar to reduced scale integration has been developed which is capable of obtaining integrated power circuits of reduced size, but operating with high levels of current and voltage. The devices obtained by this technology are known as Integrated Power Circuits (IPC). Integrated Power Circuits are currently used in any machine or device which requires a power supply which is different from the primary power supply and in which a high level of voltage, current and/or output power control is desired.
A particular category of IPC circuits known as High Voltage Integrated Circuits or HVIC includes interfaces with high voltage and relatively low current which are capable of connecting, for example, logic circuits and discrete high power devices.
Integrated circuits, and in particular high voltage transistors, can be realized using IPC technology with vertical or lateral structures. Vertical integration of high voltage transistors and of the corresponding driver circuitry however requires thick epitaxial layers or multiple layers, as well as complicated and expensive insulating dielectrics. Lateral integration of power devices is generally preferred, as this only requires a thin epitaxial layer of approximately 5-10 .mu.m thick, and this is therefore more compatible with the manufacturing processes of low voltage circuits.
In addition to this, in all applications in which inductive loads have to be controlled it is of fundamental importance to be able to limit if not in fact eliminate parasitic transistors which might originate in the vicinity of layers having the opposite type of doping.
FIG. 1 diagrammatically illustrates a prior art circuit architecture 1 which includes a driver circuit 2 inserted between a first supply reference voltage Vcc and a second reference voltage, for example, a ground GND, and connected to an inductive load L which is in turn connected to ground GND.
In order to simplify the description, driver circuit 2 in FIG. 1 will be illustrated with only two components, specifically a power transistor T1 and a bias transistor T2, cascade inserted between the supply reference voltage Vcc and the ground GND, and having control terminals B1 and B2, respectively. Transistors T1 and T2 may be of the IGBT type. Terminals B1 and B2 are connected to a circuit portion which is not shown in FIG. 1 as it is not pertinent to the operating of architecture 1.
FIG. 2 shows a cross-sectional view of the power transistor T2 in driver circuit 2. The structure includes a substrate 3 of the P.sup.- type on which are provided a deep layer 4 of the N.sup.+ type and an epitaxial layer 5.
Within the epitaxial layer 5 a first diffusion zone 6 of the N.sup.- type and a second diffusion zone 7 of the P.sup.+ type, together with a third diffusion zone 8 of the N.sup.+ type located on the deep layer 4, are obtained by implantation and subsequent diffusion of the doping agent. Diffusion zone 6 includes collector terminal C1 for power transistor T2 of the driver circuit 2 and is therefore directly connected to the inductive load L.
As the current recycles within the inductive load, the potential of collector C1 is force carried to a value less than the potential of ground GND. In this way a parasitic transistor P, of which an electrical diagram is indicated superimposed as dashed lines on the section of the integrated circuit shown in FIG. 2, is thus turned on. This parasitic transistor P has an emitter terminal Ep which coincides with the third diffusion zone 8, and a collector terminal Cp which coincides with the first diffusion zone 6, and a control or base terminal Bp which coincides with the substrate 3 of the integrated circuit. Parasitic transistor P is therefore a lateral transistor of the NPN type.
The current gain in this transistor may vary according to the arrangement and the area of the diffusion wells in the device. The presence of this parasitic transistor generally interferes with correct operation of the integrated circuit. This becomes a very serious problem for applications with high supply voltages, i.e., values in excess of 500 V.
A known technical solution for eliminating this parasitic transistor is illustrated in FIG. 3. In addition to power transistor T2, FIG. 3 shows other diffusion zones 7' and 8', as well as a deep region 4', realized within the epitaxial layer 5, which include components of the integrated circuit adjacent to power transistor T1.
The known solution provides for the use of a structure 9, a so-called barrier structure, placed between the area in which power transistor T1 is formed and the areas which include the adjacent circuits. Barrier 9 collects most of the current provided by emitter terminal Ep of parasitic transistor P.
Although fulfilling its object, this solution needs an appreciable area of integrated circuit for its implementation, thus countering the efforts made to obtain a high integration density for power devices too.
Other known solutions are obtained using a thin epitaxial technique, which presents problems with the integration of structures which are operating at high voltage levels and are at the same time safe as regards polarity reversals. In thin epitaxial technology it is not in fact possible to obtain integrated structures with a low loss toward the substrate.